Successful ESD control programs depend on knowledgeable personnel for their successful implementation and maintenance. Knowing that their employees, present and prospective, can handle ESD issues increases employers’ confidence in their processes and products. Certification validates the ESD professional’s efforts and abilities and ensures both employer and customers of commitment and credibility.

The ESD Association (ESDA) offers two types of professional certification:

• ESD Certified Professional – Program Manager, and

• ESD Certified Professional – Device/Design Certification

The ESD Certified Professional-Program Manager certification, introduced in 2003, was developed for persons actively involved in implementing, managing, and auditing ESD control programs in their facilities. It is also suitable for consultants; and even sales personnel of ESD ESD control products suppliers.

Shortly after the Program Manager certification was introduced, the ESD Association developed a second certification to meet the needs of the technical community. The ESD Certified Professional-Device/Design certification was created specifically for individuals responsible for ESD protection in circuit design.

Certification Requirements

Each certification program has the following steps:

1. Application: Open an official file in your name with ESD Association Headquarters.

2. Preparation: Complete the minimum pre-requisite courses related to the chosen certification program.

3. Examination: Pass the in-depth examination. The exam is open book and contains both multiple choice and essay questions.

4. Ongoing Professional Activity: Maintain certification by fulfilling the continuing education requirement. Certification stands for a continued commitment to learning and professional growth.

Specific Course Requirements

A primary goal of ESD certification is effective training. The courses required for certification have been developed and are taught by ESD Association instructors who work in the field directly with the issues they teach. Course material is updated as changes in the field demand.

The following are the courses applicable to each certification program. Course lengths run from half a day to two days. If an individual has completed a required course in 2003 or following years, it may be credited towards the requirements of a certification program.

Courses for ESD Certified Professional-Program Manager Certification Program

• ESD Program Development & Assessment (ANSI/ESD S20.20 Seminar). This two-day seminar provides instruction on designing and implementing an ESD control program based on ANSI/ESD S20.20-1999. The course provides participants with the tools and techniques to prepare for an ESD facility audit.

• ESD Basics for the Program Manager. This full-day tutorial consists of three sections, which define the causes of ESD and critical elements related to charge generation, material characteristics and electrostatic phenomenon; explain and demonstrate the four critical device failure models; provide an overview of device protection during handling and product assembly; summarize ESD control elements; and provide a fundamental overview of S20.20 program requirements.

• Air Ionization: Issues and Answers. This half-day seminar examines problems caused by static charges; reviews common methods for generation and control of static charge; illustrates the importance of ionizers in a static control program through demonstrations; explains the major types of ionizers and the varying environments; discusses electrical and performance test methods; demonstrates ionization measurements using the ionization standard ANSI/ESD STM3.1-2000 Ionization, presents installation, safety, maintenance, and contamination issues; and analyzes case histories of the use of ionizers in a variety of work environments.

• How To’s of In-Plant ESD Auditing and Evaluation Measurements. This full-day program was designed to support ANSI/ESD S20.20-1999 in-plant verification requirements. It reviews the evaluation and audit measurement procedures for S20.20 ESD controls listed in the S20.20 document, “Table 1-ESD Control Program Technical Requirements Summary.” These recommended measurement procedures confirm the proper operation and use of ESD control products and materials selected as part of an ANSI/ESD S20.20-1999 based ESD control program.

• Packaging Principles for the Program Manager. This half-day seminar focuses on the packaging and handling standard, ANSI/ESD S541-2003. This standard is a revision of the now obsolete industry standard EIA 541-1988. Shipping and handling of parts, both internal to a factory, and externally to distributors or end users has always been an area of risk in the manufacturing process. The standard and the seminar provide information and guidance, as well as material specifications, to assist in the design and implementation of a packaging plan for use within an ANSI/ESD S20.20-1999 based ESD control program.

• ESD Standards Basics for EPA. This half-day standards tutorial provides an overview of all the standards, grouped into common test method types based on measurement probe and test instruments. This tutorial covers the requirements, applications, and specifications for each standard and standard test method.

• Device Technology and FA Overview. This half-day tutorial provides a broad overview of ESD device technology, the ways circuit designers protect against ESD, and the failure analysis techniques that are likely to be encountered in reports about ESD failures. This course is not intended to turn participants into ESD protection designers or a failure analysis engineers but provides a background on what designers and failure analysis engineers actually do. After completing this tutorial participants should be able to understand the basics of device protection design and some of the trade-offs inherent in that process.

• Electrostatic Calculations for the ESD Engineer. This half-day tutorial focuses on the basic calculations and techniques of use to the ESD engineer. The content is at the sophomore physics or electrical engineering level set in the context of electrostatic discharge and its effects. Topics covered include Gauss’ Law, capacitance, charge sharing, RC decay, and device failure thresholds.

• Cleanroom Considerations for the Program Manager. This half-day tutorial provides a detailed review of the following concepts: cleanroom/clean environment function, airborne particle classification standards, cleanroom compliance monitoring test methodologies, electrostatic attraction in relation to airborne and surface contamination, electrostatic discharge concerns, and cleanroom static charge generation challenges and control methodologies.

• System Level ESD/EMI, Part 1: Principles, Design Troubleshooting, and Demonstrations is a half-day course that covers the following topics: characteristics of ESD events, ESD principles as applied to electronic systems, design troubleshooting techniques, unusual forms of ESD that have been the cause of field failures including internal chair discharges, high frequency measurement techniques, and system design principles.

• System Level ESD/EMI Part 2: Testing to IEC and Other Standards is a half day tutorial intended to help those tasked with testing products to IEC and other system level ESD standards by providing detailed information on IEC 61000-4-2, the most widely used standard, and highlighting the harmonization and differences between IEC, ANSI, Telcordia, and some automotive ESD standards. Common questions regarding test setups, test points and procedures are answered and key issues are addressed. Those attending this tutorial section should have had at least one year of a college level electronic circuits course. Knowledge of common circuit analysis techniques is assumed.

Courses for ESD Certified Professional-Device/Design Certification Program

• ESD On-Chip Protection in Advanced Technologies. This tutorial addresses important issues in the design of IC protection circuits built with advanced deep sub-micron CMOS technologies, including silicon-on-insulator (SOI) and high voltage MOSFETs. The full-day tutorial presents fundamental aspects of ESD protection design such as basic NMOS and SCR concepts, as well as gate-biased and substrate driven NMOS protection concepts. Protection design methods to meet the human body model (HBM), machine model (MM), and charged device model (CDM) are presented. Other topics covered include BiCMOS protection circuits, mixed voltage protection, and compatibility to latch-up. This tutorial is useful for design, device, process, product, failure analysis, and reliability engineers and assists those attending other design related tutorials. Attendees should have a minimum knowledge of MOS device operation in integrated circuits.

• System Level ESD/EMI (2 Parts) This course is also required for the Program Manager certification. The full course description is given above.

• On-Chip ESD Protection in RF Technologies. In this half-day tutorial, ESD protection in radio frequency (RF) technologies is discussed, including ESD protection in RF CMOS, BiCMOS silicon germanium, gallium arsenide, and RF silicon-on-insulator (SOI). This tutorial focuses on device physics, technology, ESD layout design, ESD circuits and design systems. Also, HBM (Human Body Model), MM (Machine Model), and TLP (Transmission Line Pulse) measurements of RF ESD technologies and RF circuits are discussed.

• SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits. This half-day tutorial explores each of the key elements in typical active ESD networks, including diodes, power busses, and active clamp devices with trigger circuits, and reviews approaches for ESD-hardening of fragile output driver transistors. A step-by-step methodology for SPICE-based ESD network design and optimization is introduced. Also, the flexibility of active ESD networks is demonstrated in a wide range of IC application examples.

• EOS/ESD Failure Models and Mechanisms. Fundamental failure mechanisms of electrical overstress/electrostatic discharge and the physics behind them are the focus of this half-day tutorial. Topics include the primary thermal failure mechanisms: junction burnout, oxide punch-through, and metallization burnout. Particular emphasis is placed on the concept of simulation fidelity, which is crucial in the design of meaningful and robust ESD tests.

• Circuit Modeling and Simulation for On-Chip Protection. This tutorial, which is approximately a half-day in length, addresses modeling and simulation of protection circuit elements and networks under ESD conditions. The high current characteristics and transient responses of devices typically used in ESD protection circuits are presented. The objective is to ascertain what behaviors have to be captured in models intended for circuit-level simulation of ESD. This tutorial assumes some familiarity with device physics and is directed toward persons with an interest in the transistor-level physics of ESD in on-chip protection circuits and an in computer-aided design.

• Latch-up Physics and Design. Latch-up continues to be of interest today in advanced CMOS, mixed signal (MS) CMOS, RF CMOS, BiCMOS, and BiCMOS silicon germanium. This approximately half-day long latch-up tutorial provides a discussion on device-level latch-up physics; latch-up metrics and design criteria; latch-up test structures; test methods; latch-up measurement techniques; device-level CAD simulation; and new latch-up issues. Both internal and external latch-up phenomenon, as well as DC and transient latch-up, are addressed. Latch-up structures, guard ring physics, and characterization will be discussed in depth.

• Troubleshooting On-Chip ESD Failures. Diagnosing and fixing on-chip ESD product qualification failures can often be one of the more challenging aspects of work in ESD. The pressure to quickly find and correct an HBM/MM/ CDM failure to qualify a product often compounds the inherent difficulty of troubleshooting. Experience diagnosing failures, though not desirable from a product qualification standpoint, can greatly improve troubleshooting skills. This half-day tutorial builds troubleshooting experience and skills by presenting case studies of actual on-chip HBM failures in a workshop format. Participants analyze each failure case, interacting with the instructor to determine its root cause and a solution. The tutorial identifies common concepts, methods, and tools useful in failure diagnosis. Participants should be familiar with CMOS technology, on-chip ESD breakdown phenomena, standard ESD protection circuits, and the HBM test procedure. Participants should also be able to read circuit diagrams and have a basic understanding of the function of IO circuits.

• Transmission Line Pulse Measurements: Parametric Analyzer for ESD On-Chip Protection. This approximately half-day long tutorial explores the parameters measured with a TLP system and discusses the importance of the parameters in the design of on-chip ESD protection circuits. Circuit elements and circuits that are discussed include n- and p-MOS transistors, NPN bipolar transistors, diodes, resistors, metal runners, power supply clamps, and even full integrated circuits. Also, variations in the test structure layouts, which are important for understanding the properties of the technology, are discussed.

• Device Testing—Component Level: HBM, CDM, MM, & TLP. This tutorial addresses the basics of HBM, CDM, MM, and TLP ESD stress testing of the ESD protection structures of ICs. The differences between these models is emphasized and used to show how the different circuit parasitics affect the waveforms from each model-type simulator. The importance of doing ESD testing as an integral part of a high quality component development and qualification efforts is stressed. This tutorial covers constant impedance and constant current TLP testing and the TLP I-V characteristic plots, including the snap-back trigger voltages and currents. The evolution of the leakage current as it relates to the failure point and comparisons and correlations between HBM and TLP testing are emphasized. Standards issues and test procedures, including some comparison between the ESDA and JEDEC standards will be discussed.

• CDM Design and Characterization. This approximately half-day long course teaches the basic concepts and ideas required to design-in for Charge Device Model (CDM) ESD tests. Course topics include a brief history of CDM ESD development, charge and discharge physics, component level IC CDM testing, CDM failure mechanisms, CDM fast transient measurements, CDM circuit simulations, and CDM design-in strategies and characterization.

• Impact of CMOS Technology Scaling on ESD High Current Phenomena. This advanced tutorial covers the impact of silicon technology scaling on ESD device behavior and on consequent ESD protection design. The physics of CMOS components under high current conditions and the technology trends for sub-100nm nodes and their implications for the ESD design window are discussed. Finally, sub-50nm technologies challenges will be addressed. This approximately half-day long course is intended for students who have taken the basic on-chip protection class and are familiar with basic device physics for both ESD and latch-up.

Course Availability

The required courses are offered every year at the EOS/ESD Symposium as well as at additional times throughout the year, in North America, Europe, and Asia. The 2005 EOS/ESD Symposium will be held September 11-16, in Anaheim, California. An up-to-date education schedule is available from the ESD Association website, www.esda.org.

For individuals interested in the Device/Design certification, the ESD Association regularly offers the Device/Design Seminar, a two-day course that fulfills the requirements for the following of the above courses:

• ESD On-Chip Protection in Advanced Technologies

• SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits

• EOS/ESD Failure Models and Mechanisms

• CDM Design and Characterization

This year the Device/Design seminar will be available in at ESDA Headquarters in Rome, NY, in May, and in June in Munich, Germany.

Exams

The ESD Association is offering the first ESD Certified Professional-Program Manager certification exam at the annual symposium, on Friday, September 16, 2006, in Anaheim, California. To take this exam an official registration filing fee of $50.00 and a registration form must be completed and submitted to ESDA Headquarters. You must have taken all of the required courses and have your eligibility verified by the ESDA. An exam fee will be applicable. The first ESD Certified Professional-Device/Design exam will be held at the 2006 EOS/ESD Symposium in Tucson, Arizona.

The ESDA is offering National Association of Radio and Telecommunications Engineers (NARTE) certified ESD engineers the opportunity to take the ESD Certified Professional-Program Manager exam without having to take all of the required courses. Simply show your current NARTE card, pay the exam fee, and take the exam. Please note that the Program Manager exam does cover additional areas and may be more difficult than the NARTE exam. n

About the ESD Association

Founded in 1982, the ESD Association is a not for profit, professional organization dedicated to furthering the technology and understanding of electrostatic discharge. The Association sponsors educational programs, develops ESD standards, holds an annual technical symposium, and fosters the exchange of technical information among its members and others. Additional information may be obtained by contacting the ESD Association, 7900 Turin Rd., Bldg. 3, Rome, NY 13440-2069 USA. Phone: 315-339-6937. Fax: 315-339-6793. Email: info@esda.org. Website: http://www.esda.org.