From ESD Introduction ESD Generators are commonly calibrated using a 2-ohm ESD Current Target, such as is detailed in IEC 61000-4-2. Although the IEC 61000-4-2 Current Target is an excellent design, it is rather complex with six custom-machined components and a printed circuit board (PCB). The Embedded Current Target design we present here consists of one two-layer PCB and uses no machined parts.
Usage ESD Current Targets are used in the setup shown in Figure 1. The 2-ohm ESD Target produces a voltage waveform that is proportional to the ESD Gun current waveform. The 20-dB pad reduces ripple in the frequency domain response. The coaxial cable connecting the Target to the Oscilloscope should be short and of high quality to minimize attenuation of the ESD pulse leading edge.
Figure 1
IEC 61000-4-2 Current Target Specifications The IEC 61000-4-2 Current Target Specifications are listed below. The Embedded Current Target S21 was measured with an Agilent 8753ES VNA and the results are plotted in Figure 2. The Embedded Current Target exceeds the IEC 61000-4-2 specifications by a good margin, exhibiting a peak-to-peak variation of only 0.1 dB to 1 GHz and 0.5 dB to 4 GHz.
Figure 2: Embedded Current Target and Mini-circuits BW-320W2 attenuator S21 plot
Embedded Current Target Although simple in design, the Embedded Current Target is able to exceed the IEC specifications by using embedded resistors. Rather than mounting the resistors on the PCB top layer, the resistors are mounted inside the circuit board, as shown in Figure 3. Embedding the resistors, and placing the current-return vias nearby, reduces the effective resistor inductance by roughly 50%. The low inductance results in less high frequency peaking and improved waveform fidelity. Figure 4 shows the current paths with red representing the input (high current) path and blue representing the output (low current) path. The coupled inductors represent the resistors and adjacent vias. Note that the output path has a Kelvin-like connection to the embedded resistors.
Figure 3
Figure 4
The Embedded Current Target is much like the IEC 61000-4-2 Current Target in that twenty-four 51-ohm resistors are placed symmetrically about the center of the target, forming a 2-ohm current sensing resistor (Figure 5). The Embedded Current Target has the 0603 resistors placed into holes (shown as white) and soldered in place. The resistor holes are actually oblong and are made by a milling operation. The 62-mil thick board allows the 0603 resistor ends to be flush with the board surface. To avoid having to mill an oblong hole, cylindrical SMT resistors (Venkel LTD TNR50 series) can be used and placed into circular holes.
Figure 5
Calibration Although IEC 61000-4-2 recommends that a conical line adapter, or an APC-7 connector, be placed symmetrically on the target for calibration, we found that placing a Microwave probe at the perimeter of the disk works well. SPICE simulation shows that the perimeter probe masks approximately 0.5 dB of peaking at 4 GHz. The simulated peaking effect on a 0.25 ns rise-time ESD pulse is shown in Figure 6; The red trace is the simulated time-domain response using an ideal conical line adapter and the blue trace is the simulated response using a Microwave probe at the perimeter of the disk.
Figure 6
Further Possible Improvements The upper frequency limit of the Embedded Current Target can be improved by shrinking the dimensions. By embedding 0201 resistors in a 20 mil thick PCB, the resistor inductance can be reduced by a factor-of-three along with the PCB parasitics. The central disk radius can be reduced from 5 mm to 2.5 mm, allowing an SMA connector to be positioned centrally for calibration. n
References IEC 61000-4-2, (EMC): TESTING AND MEASUREMENT TECHNIQUES – ELECTROSTATIC DISCHARGE IMMUNITY TEST, Appendix B
Reference Data for Radio Engineers, Sixth Ed., ITT
UPDATE ON ESD TESTING ACCORDING TO IEC 61000-4-2 Thomas C. Moyer and Rodger Gensel, Amplifier Research and Harald Kunkel, EM Test
Metrology & Methodology of System Level ESD Testing Don Line, Lucent Technologies D. Pommerenke, Hewlett Packard J. Barth, Barth Electronics L.G. Henry, AMD H. Hyatt, Hyger Physics Inc. M. Hopkins and G. Senko, Keytek D. Smith, Auspex Systems
About the Authors Robert Casiano is a Senior Engineering Technician specializing in high-speed design at Micron Technology in Boise, Idaho.
David Cuthbert is the QRA Signal Integrity Manager and a Micron Fellow at Micron Technology in Boise, Idaho. He is a NARTE certified EMC Engineer. © Copyright 2007 Conformity |
